A wafer level bumping process involves the formation of electrically conductive bumps upon terminals of electronic components while still in wafer form. Subsequently, the bumps are use to form electrical interconnections with the electronic components.
If the wafer is warped, unevenness in the height of the bumps is created. This unevenness can cause open circuits and thus reworking or scrapping of the assemblies formed with the electronic components. Accordingly, it is desirable that the wafer is flat such that the bumps lie in a common plane to ensure that reliable electrical interconnections are formed with the bumps.
In the following description, the same or similar elements are labeled with the same or similar reference numbers.